1. Field of the Invention
The present invention relates to a technique which facilitates verifying the correctness of a circuit design. More specifically, the present invention relates to a technique that automatically generates an input sequence for a circuit design using mutant-based verification.
2. Related Art
Digital circuit design methodologies have reached a highly optimized state, but circuit verification methods used in design projects are still somewhat subjective in the way that they are applied by the verification engineer. Moreover, many competing circuit verification methods are available for high-level hardware descriptions, but none of these methods provide a stand-alone solution. As a result, circuit verification is still an “art” which is mastered by an engineer through experience and observation, as opposed to a systematic technique that can be easily and effectively applied.
Typical industry practices rely on random and pseudo-random approaches to eventually explore a sufficient portion of the circuit under verification (CUV). The simplicity in these practices allows for a high-frequency simulation, but the ability of the simulator to traverse new architectural states quickly diminishes over time. Deterministic practices, on the other hand, guarantee continued forward progress because they allow the circuit verification engineer to attack the problem head-on. However, the complexity of even moderately-sized circuits makes deterministic verification practices that exhaustively explore the design space computationally infeasible in a reasonable timeframe.
Hence, what is needed is a method and an apparatus for efficiently verifying circuit designs without the problems listed above.